Method and apparatus for performing addressing operations in a superscalar, superpipelined processor

ABSTRACT

A method and apparatus for improving the performance of a superscalar, superpipelined processor by identifying and processing instructions for performing addressing operations is provided. The invention heuristically determines instructions likely to perform addressing operations and assigns those instructions to specialized pipes in a pipeline structure. The invention can assign such instructions to both an execute pipe and a load/store pipe to avoid the occurrence of “bubbles” in the event execution of the instruction requires the calculation capability of the execute pipe. The invention can also examine a sequence of instructions to identify an instruction for performing a calculation where the result of the calculation is used by a succeeding load or store instruction. In this case, the invention controls the pipeline to assure the result of the calculation is available for the succeeding load or store instruction even if both instructions are being processed concurrently.

TECHNICAL FIELD OF THE INVENTION

[0001] The invention relates generally to computer architectures andmore specifically to the management of pipelining in a superscalar,superpipelined processor.

BACKGROUND OF THE INVENTION

[0002] Superscalar processors allow the execution of multipleinstructions simultaneously. Historically, computer software has beengenerally programmed as a sequence of instructions, with eachinstruction to be executed before the one that succeeds it. However, ifa processor executes the instructions serially, one instruction at atime, the performance of the processor is limited. Thus, superscalarprocessors provide performance improvements by executing severalinstructions at once.

[0003] A technique known as pipelining is used in superscalar processorsto increase performance. Pipelining provides an “assembly line” approachto executing instructions. The execution of an instruction is dividedinto several steps. A superscalar processor is provided with a number ofstages. Each stage performs a step in the execution of the instructions.Thus, while one step in the execution of one instruction is beingperformed by one stage of the processor, another step in the executionof another instruction may be performed by another stage of theprocessor. Since the execution of several instructions can be staggeredacross several stages, it is possible to begin a new instruction everyclock cycle, even if the instructions require several clock cycles to becompleted.

[0004] However, it is often necessary to know the result of oneinstruction before executing the instruction that succeeds it. If apipelined superscalar processor attempts to execute an instruction forwhich antecedent instructions have not yet been fully executed, thepipeline may be forced to stop and wait until all antecedent conditionsfor the execution of the instruction have been met.

[0005] Superpipelining refers to pipelining using pipes with more thanfive stages. Superpipelining extends the benefits of pipelining, butincreases the potential for delays caused by dependencies betweeninstructions. Thus, a pipe may be forced to stop and wait several clockcycles in order to satisfy a dependency based on an instruction beingprocessed in another pipe.

[0006] While a pipeline structure may be optimized for certainconditions, it is extremely difficult to optimize performance for allpossible sequences of instructions. Thus, a technique is needed thatimproves pipeline performance beyond the level that can be achieved bychanges to the pipeline structure.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007]FIG. 1 is a block diagram illustrating a plurality of pipesaccording to an embodiment of the invention.

[0008]FIG. 2 is a block diagram illustrating instruction issuing logicin relation to a plurality of pipes according to the invention.

[0009]FIG. 3 is a flow diagram illustrating a method according to anembodiment of the invention.

[0010]FIG. 4 is a flow diagram illustrating a method for identifying aninstruction as being an instruction for performing addressing operationsaccording to an embodiment of the invention.

[0011]FIG. 5 is a flow diagram illustrating a process according to anembodiment of the invention.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

[0012] A method and apparatus for improving the performance of asuperscalar, superpipelined processor by identifying and processinginstructions for performing addressing operations is provided. Theinvention heuristically determines instructions likely to performaddressing operations and assigns instructions to specialized pipes in apipeline structure based on this determination. The invention can assignsuch instructions to either an execute pipe or a load/store pipe, or toboth an execute pipe and a load/store pipe, to improve performance. Byassigning the instructions to both an execute pipe and a load/storepipe, an address to be used by a subsequent instruction can becalculated by the load/store pipe before the execute pipe has completedcalculation of the address, thereby reducing delay in the execution ofthe subsequent instruction and improving performance. The invention canalso examine a sequence of instructions to identify an instruction forperforming a calculation where the result of the calculation is used bya succeeding load or store instruction. In this case, the inventioncontrols the pipeline to assure the result of the calculation isavailable for the succeeding load or store instruction.

[0013] A load/store (load or store) instruction may be referred to as atransfer instruction. Likewise, a load/store pipe may be referred to asa transfer pipe.

[0014]FIG. 1 is a block diagram illustrating a plurality of pipesaccording to an embodiment of the invention. The plurality of pipesincludes execute 0 pipe 109, load pipe 119, store pipe 129, and execute1 pipe 139. Execute 0 pipe 109, which is an example of an execute pipe,includes fetch stage 101, decode stage 102, issue stage 103, skew 1stage 104, skew 2 stage 105, read register file stage 106, execute stage107, and write register file stage 108. At fetch stage 101, aninstruction is fetched from memory. At decode stage 102, the instructionis decoded to determine the operation that is to be performed by theprocessor.

[0015] At issue stage 103, the instruction is issued to a pipe forprocessing. For example, an instruction fetched in fetch stage 101 anddecoded in decode stage 102 may be issued in issue stage 103 to any ofexecute 0 pipe 109, load pipe 119, store pipe 129, or execute 1 pipe139. Since the instruction would already be fetched and decoded, theinstruction could be issued to skew 1 stage 104, address generationstage 114, address generation stage 124, or skew 1 stage 134.

[0016] Assuming the instruction were issued to execute 0 pipe 109, theinstruction would be processed according to the remaining stages ofexecute 0 pipe 109. At skew 1 stage 104, a delay of one clock cycle isprovided to maintain synchronization with load pipe 119 and store pipe129, thereby avoiding a “bubble” condition for certain sequences ofinstructions. A “bubble” condition occurs when, as a result of adependency between instructions being processed by different pipes ofthe pipeline structure, information needed for the processing of aninstruction in one pipe has not yet been made available by another pipe.Steps that do not perform any actual operation, referred to as “nooperation” steps, or simply NOP's, are inserted in the pipe to delay theprocessing until the dependency can be accommodated. At skew 2 stage105, another delay of one clock cycle is provided.

[0017] At read register file stage 106, any register files required tobe read as operands of the instruction are read. At execute stage 107,the operation indicated by the instruction is performed, therebygenerating a result. At write register file stage 108, the result iswritten to the appropriate register file, for example, as indicated bythe instruction.

[0018] Load pipe 119, which is an example of a load/store pipe, includesfetch stage 111, decode stage 112, issue stage 113, address generationstage 114, translation lookaside buffer lookup stage 115, read datastage 116, write register file stage 117, and null stage 118. Fetchstage 111, decode stage 112, and issue stage 113 are essentiallyidentical to fetch stage 101, decode stage 102, and issue stage 103. Inaddress generation stage 114, a virtual address is generated based onoperands provided with the instruction. In translation lookaside bufferlookup stage 115, a translation lookaside buffer lookup is performed todetermine a physical address based on the virtual address. In read datastage 116, data are read from a cache memory at a location specified bythe physical address. In write register file stage 117, the data arewritten to a register file, as specified by the operands of theinstruction.

[0019] Store pipe 129, which is an example of a type of load/store pipe,includes fetch stage 121, decode stage 122, issue stage 123, addressgeneration stage 124, translation lookaside buffer stage 125, readregister file stage 126, null stage 127, and write data stage 128. Fetchstage 121, decode stage 122, and issue stage 123 are essentiallyidentical to fetch stage 101, decode stage 102, and issue stage 103. Inaddress generation stage 124, a virtual address is generated based onoperands provided with the instruction. In translation lookaside bufferlookup stage 115, a translation lookaside buffer lookup is performed todetermine a physical address based on the virtual address. In readregister file stage 126, data are read from a register file, asspecified by the operands of the instruction. In null stage 127, noaction need be taken. Null stage 127 may be used to provide a delay tomaintain synchronization among the pipes, or it may be omitted. In writedata stage 128, the data are written to a cache memory at a locationspecified by the physical address.

[0020] Execute 1 pipe 139, which is an example of an execute pipe,includes fetch stage 131, decode stage 132, issue stage 133, skew 1stage 134, skew 2 stage 135, read register file stage 136, execute stage137, and write register file stage 138. Fetch stage 131, decode stage132, and issue state 133 are essentially identical to fetch stage 101,decode stage 102, and issue stage 103. In skew stage 134, a delay of oneclock cycle is provided to maintain synchronization with load pipe 119and store pipe 129, thereby avoiding a “bubble” condition for certainsequences of instructions. In skew 2 stage 135, another delay of oneclock cycle is provided.

[0021] At read register file stage 136, any register files required tobe read as operands of the instruction are read. At execute stage 137,the operation indicated by the instruction is performed, therebygenerating a result. At write register file stage 138, the result iswritten to the appropriate register file, for example, as indicated bythe instruction.

[0022] By providing skew 1 stage 104 and skew 2 stage 105 in Execute 0pipe 109 and skew 1 stage 134 and skew 2 stage 135 in Execute 1 pipe139, certain sequences of instructions that are interdependent may beco-issued without requiring a pipe to stop processing to accommodate thedependencies. For example, if a load or store instruction is followed byan execute instruction that uses the value loaded or stored according tothe load or store instruction, both the load or store instruction andthe execute instruction that follows it can be issued at the same timeto different pipes of the pipeline structure. By issuing the load orstore instruction to a load/store pipe and issuing the executeinstruction to an execute pipe, the skew stages in the execute pipesstagger the execute pipes relative to the load/store pipes so that thevalue loaded or stored is ready in time for it to be used in an executepipe without causing the execute pipe to stop.

[0023] However, while the introduction of skew stages improvesperformance of a superscalar, superpipelined processor when executing aload or store instruction followed by an execute instruction that usesthe value loaded or stored according to the load or store instruction,it complicates execution of other sequences of instructions. Forexample, when an execute instruction is followed by a load or storeinstruction, where an address used by the load or store instruction iscalculated by the execute instruction, not only does a delay normallyoccur while the execute instruction is processed before the load orstore instruction can be processed, but the delay is increased by theskew stages. This delay detrimentally affects performance.

[0024] An embodiment of the invention avoids the delay described aboveby enabling a load or store pipe to calculate the address used by theload or store instruction before the processing of the executeinstruction is completed in the execute pipe. Thus, processing of theload or store instruction can be completed without waiting forprocessing of the execute instruction to be completed. Thus, theinvention avoids the delay of described previously.

[0025]FIG. 2 is a block diagram illustrating instruction issuing logicin relation to a plurality of pipes according to the invention.Instruction issuing logic 205 is illustrated in relation to execute 0pipe 201, load/store 0 pipe 202, load/store 1 pipe 203, and execute 1pipe 204. Instruction issuing logic 205, execute 0 pipe 201, load/store0 pipe 202, load/store 1 pipe 203, and execute 1 pipe 204 are includedwithin superscalar, superpipelined processor 207. Instruction issuinglogic 205 is operatively coupled to execute 0 pipe 201, load/store 0pipe 202, load/store 1 pipe 203, and execute 1 pipe 204. Execute 0 pipe201, load/store 0 pipe 202, load/store 1 pipe 203, and execute 1 pipe204 may also be operatively coupled to each other, as indicated byconnections 206. The instruction issuing logic 205 issues to aload/store pipe, such as load/store 0 pipe 202 or load/store 1 pipe 203,an instruction likely to perform an addressing operation. Otherinstructions, such as instructions for operations requiring executionare issued to an execute pipe, such as execute 0 pipe 201 or execute 1pipe 204.

[0026] The instruction issuing logic 205 heuristically determines theinstruction as being likely to perform the addressing operation. Forexample, the instruction issuing logic 205 can compare the type ofinstruction being issued against known types of instructions associatedwith addressing operations. The instruction issuing logic 205 can alsolook at the next instruction to be processed to see if the combinationof the current instruction and the next instruction are a combinationknown to be associated with addressing operations. Addressing operationsinclude operations that relate to an address, such as operations thatinvolve loading or storing a value at a particular location in a memorydevice according to an address for that particular location.

[0027] As an example, the instruction issuing logic 205 can identify theinstruction as being a short shift instruction. For example, the shortshift instruction may cause a shift of two or three bits. Such a shiftmay be interpreted as being associated with an addressing operation. Assuch, the instruction may be issued to a load/store pipe.

[0028] As another example, the instruction issuing logic 205 candetermine that the instruction is a literal instruction. A literalinstruction may be an immediate mode instruction or an instruction withvalues embedded in the instruction. Thus, it is not necessary to referto a two register locations to obtain those values. Such instructionsmay be interpreted as being associated with an addressing operation. Assuch, the instruction may be issued to a load/store pipe.

[0029] As yet another example, the instruction issuing logic 205 candetermine that the instruction is one of the following: an add immediateunsigned instruction, a dual add immediate unsigned instruction, asubtract immediate unsigned instruction, a dual subtract immediateunsigned instruction, a load upper immediate instruction, and an ORimmediate instruction.

[0030] While the instruction issuing logic 205 can issue an instructionidentified as being an instruction likely to perform an addressingoperation to a load/store pipe, the instruction issuing logic 205 canalso issue such an instruction to both an execute pipe and a load/storepipe. In that case, before the execute pipe finishes calculating aresult, the load/store pipe calculates an address and provides theaddress for use in a subsequent instruction. The instruction issuinglogic 205 can issue the instruction to both the load/store pipe and theexecute pipe during an identical clock cycle so as to maintainsynchronization between the load/store pipe and the execute pipe, or theinstruction issuing logic 205 can issue the instruction to theload/store pipe and the execute pipe during different clock cycles.

[0031]FIG. 3 is a flow diagram illustrating a method according to anembodiment of the invention. The method allows processing an instructionin a superscalar, superpipelined processor that includes a load/storepipe and an execute pipe. The method begins in step 301. In step 302, acapability in the load/store pipe to process instructions for performingaddressing operations is provided. In step 303, an instruction isidentified as being among the instructions for performing addressingoperations. This identification may be performed by heuristicallydetermining that the instruction is likely to perform an addressingoperation. In step 304, the instruction is assigned to a load/storepipe. Optionally, the instruction may be assigned to both the load/storepipe and the execute pipe. If the instruction is assigned to both theload/store pipe and the execute pipe, the instruction may be assigned toboth pipes during the same clock cycle or during different clock cycles.In step 305, the load/store pipe is used to calculate an address. Instep 306, the address calculated by the load/store pipe is used foraddressing in a load or store instruction that follows the instructionthat led to the calculation of the address in step 305. If theinstruction is assigned to the execute pipe, as well as to theload/store pipe, the process uses the execute pipe to calculate a resultin step 308. In step 309, the process updates a register file with theresult calculated in step 308. Since the execute pipe is usually longerthan the load/store pipe, steps 308 and 309 usually require more time tocomplete than steps 305 and 306. Thus, the process uses a load/storepipe to provide an address for use in a subsequent load or storeoperation before the result is available from the execute pipe. In step307, the process ends.

[0032]FIG. 4 is a flow diagram illustrating a method for identifying aninstruction as being an instruction for performing addressing operationsaccording to an embodiment of the invention. The method begins in step401. The method then identifies the instruction according to one or moreof steps 402, 403, and 404. In step 402, a determination is made as towhether the instruction is a short shift instruction. For example, theinstruction may be identified as a short shift instruction that resultsin shifting by two bits or four bits. In step 403, a determination ismade as to whether the instruction is a literal instruction. In step404, a determination is made as to whether the instruction is one of thefollowing: an add immediate unsigned (ADD i/u) instruction, a dual addimmediate unsigned (DADD i/u) instruction, a subtract immediate unsigned(SUB i/u) instruction, a dual subtract immediate unsigned (DSUB i/u)instruction, a load upper immediate (LUI) instruction, or an ORimmediate (ORI) instruction. The method ends in step 405. The steps ofthis method, as denoted by region 406, may be used to implement step 303of the process of FIG. 3. Some or all of steps 402, 403, and 404 may becombined to allow testing for short shift instructions, literalinstructions, ADD i/u, DADD i/u, SUB i/u, DSUB i/u, LUI, or ORIinstructions, or any combination thereof.

[0033] In one embodiment of the invention, if an instruction such as anADD i/u, DADD i/u, SUB i/u, DSUB i/u, LUI, or ORI is followed by aconsuming load or store instruction, an execute pipe and two load/storepipes can be used to improve performance. A consuming load or storeinstruction is a load or store instruction that relies on the result ofthe ADD i/u, DADD i/u, SUB i/u, DSUB i/u, LUI, or ORI instruction. Inthe event that a consuming load or store instruction follows one ofthese instructions, one load/store pipe is used to perform the actualload or store instruction, while the other load/store pipe is used tocalculate the operands of the load/store instruction, including anycalculation to be performed by the ADD i/u, DADD i/u, SUB i/u, DSUB i/u,LUI, or ORI instruction upon which the operands of the load/storeinstruction depend.

[0034] The execute pipe is used to perform the calculation of the ADDi/u, DADD i/u, SUB i/u, DSUB i/u, LUI, or ORI instruction and to updateany register that is changed as a result of the ADD i/u, DADD i/u, SUBi/u, DSUB i/u, LUI, or ORI instruction. Since the load/store pipes canbe shorter than the execute pipe, the load/store pipes can provide thecalculations of the ADD i/u, DADD i/u, SUB i/u, DSUB i/u, LUI, or ORIinstruction for use in the load or store operation before the processingof the ADD i/u, DADD i/u, SUB i/u, DSUB i/u, LUI, or ORI instruction bythe execute pipe is completed. Any other non-addressing operations thatrequire the results of the ADD i/u, DADD i/u, SUB i/u, DSUB i/u, LUI, orORI instruction can obtain those results after processing of theinstruction is completed by the execute pipe.

[0035] If the ADD i/u, DADD i/u, SUB i/u, DSUB i/u, LUI, or ORIinstruction is not followed by a consuming load or store instruction,the action taken depends on the state of the load/store pipe and theexecute pipe. If the load/store pipe is busy and the execute pipe isbusy, no action is taken until either pipe is no longer busy. If theload/store pipe is busy, but the execute pipe is ready, execution of theinstruction proceeds in the execute pipe.

[0036] If the load/store pipe is ready, but the execute pipe is busy,the instruction is processed using the load/store pipe if all theoperands are ready. If not all operands are ready, no action is takenuntil the situation changes. If both the load/store pipe and the executepipe are ready, the instruction is processed using the load/store pipeif all the operands are ready. If not all operands are ready, theinstruction is processed using the execute pipe.

[0037] In an embodiment of the invention, the above actions occurregardless of whether or not the ADD i/u, DADD i/u, SUB i/u, DSUB i/u,LUI, or ORI instruction is followed by a consuming load or storeinstruction. By not having to analyze any instructions following the ADDi/u, DADD i/u, SUB i/u, DSUB i/u, LUI, or ORI instruction, unnecessarycomplexity is avoided.

[0038]FIG. 5 is a flow diagram illustrating a process according to anembodiment of the invention. The process begins in step 501. In step502, a decision is made as to whether or not the load/store pipe isready. If the load/store pipe is ready, the process continues to step503. In step 503, a decision is made as to whether or not all operandsare ready. If so, the instruction is issued to the load/store pipe instep 504. The process then ends in step 507.

[0039] If the load/store pipe is not ready in step 502 or not alloperands are ready in step 503, the process continues to step 505. Instep 505, a decision is made as to whether or not the execute pipe isready. If the execute pipe is not ready, the process returns to step502. If the execute pipe is ready, the process continues to step 506. Instep 506, the instruction is issued to the execute pipe. The processthen ends in step 507.

[0040] It is understood that the load/store pipe and the execute pipereferenced with respect to FIG. 5 may be practiced with multipleload/store pipes and/or multiple execute pipes. An instruction may beissued to any suitable load/store pipe and/or execute pipe that isready, provided the conditions of FIG. 5 are met.

[0041] Thus, a method and apparatus for improving the performance of asuperscalar, superpipelined processor by identifying and processinginstructions for performing addressing operations has been provided.

What is claimed is:
 1. A method for processing an instruction in asuperscalar, superpipelined processor that includes a load/store pipeand an execute pipe, the method comprising steps of: providing acapability in the load/store pipe to process instructions for performingaddressing operations; identifying the instruction as being among theinstructions for performing addressing operations; assigning theinstruction to the load/store pipe.
 2. The method of claim 1 wherein thestep of identifying the instruction as being among the instructions forperforming addressing operations includes the step of: heuristicallydetermining that the instruction is likely to perform an addressingoperation.
 3. The method of claim 2 wherein the step of heuristicallydetermining that the instruction is likely to perform the addressingoperation comprises the step of: identifying the instruction as being ashort shift instruction.
 4. The method of claim 3 wherein the shortshift instruction results in shifting by two bits.
 5. The method ofclaim 3 wherein the short shift instruction results in shifting by threebits.
 6. The method of claim 2 wherein the step of heuristicallydetermining that the instruction is likely to perform the addressingoperation comprises the step of: determining that the instruction is aliteral instruction.
 7. The method of claim 2 wherein the step ofheuristically determining that the instruction is likely to perform theaddressing operation comprises the step of: determining that theinstruction is among a group consisting of: an add immediate unsignedinstruction; a dual add immediate unsigned instruction; a subtractimmediate unsigned instruction; a dual subtract immediate unsignedinstruction; a load upper immediate instruction; and an OR immediateinstruction.
 8. The method of claim 1 wherein the step of assigning theinstruction to the load/store pipe further comprises the step of:assigning the instruction to both the load/store pipe and the executepipe.
 9. The method of claim 8 further comprising the steps of: usingthe load/store pipe to calculate an address; and using the addresscalculated by the load/store pipe for addressing in a load/storeoperation.
 10. The method of claim 9 wherein the step of assigning theinstruction to both the load/store pipe and the execute pipe causes theinstruction to be assigned to both the load/store pipe and the executepipe during an identical clock cycle.
 11. A superscalar, superpipelinedprocessor comprising: an execute pipe; a load/store pipe; andinstruction issuing logic operatively coupled to the execute pipe and tothe load/store pipe to issue to the load/store pipe an instructionlikely to perform an addressing operation.
 12. The superscalar,superpipelined processor of claim 11 wherein the instruction issuinglogic heuristically determines the instruction as being likely toperform the addressing operation.
 13. The supersealar, superpipelinedprocessor of claim 11 wherein the instruction issuing logic identifiesthe instruction as being a short shift instruction.
 14. The superscalar,superpipelined processor of claim 13 wherein the short shift instructionresults in shifting by two bits.
 15. The superscalar, superpipelinedprocessor of claim 13 wherein the short shift instruction results inshifting by three bits.
 16. The superscalar, superpipelined processor ofclaim 11 wherein the instruction issuing logic determines that theinstruction is a literal instruction.
 17. The superscalar,superpipelined processor of claim 11 wherein instruction issuing logicdetermines that the instruction is among a group consisting of: an addimmediate unsigned instruction; a dual add immediate unsignedinstruction; a subtract immediate unsigned instruction; a dual subtractimmediate unsigned instruction; a load upper immediate instruction; andan OR immediate instruction.
 18. The superscalar, superpipelinedprocessor of claim 11 wherein the instruction issuing logic issues toboth the issue pipe and the load/store pipe the instruction likely toperform an addressing operation.
 19. The superscalar, superpipelinedprocessor of claim 18 wherein the execute pipe calculates a result andthe load/store pipe stores the result.
 20. The superscalar,superpipelined processor of claim 19 wherein the instruction issuinglogic issues the instruction to both the load/store pipe and the executepipe during an identical clock cycle.
 21. A method for processing aninstruction in a superscalar, superpipelined processor that includes aload/store pipe and an execute pipe, the method comprising steps of:determining whether the load/store pipe is ready; determining whetheroperands are ready; and if the load/store pipe is ready and the operandsare ready, issuing the instruction to the load/store pipe.
 22. Themethod of claim 21 further comprising the steps of: determining if anexecute pipe is ready; if the load/store pipe is not ready, but theexecute pipe is ready, issuing the instruction to the execute pipe; andif the load/store pipe is ready and the execute pipe is ready, but theoperands are not ready, issuing the instruction to the execute pipe. 23.The method of claim 22 further comprising the step of: if the load/storepipe is not ready and the execute pipe is not ready, waiting until apipe selected from the load/store pipe and the execute pipe is ready.24. The method of claim 22 wherein the method is initiated in responseto a heuristic determination that the instruction is likely to performan addressing operation.
 25. The method of claim 22 wherein theinstruction is a short shift instruction.
 26. The method of claim 25wherein the short shift instruction results in shifting by two bits. 27.The method of claim 25 wherein the short shift instruction results inshifting by three bits.
 28. The method of claim 22 wherein theinstruction is a literal instruction.
 29. The method of claim 22 whereinthe instruction is among a group consisting of: an add immediateunsigned instruction; a dual add immediate unsigned instruction; asubtract immediate unsigned instruction; a dual subtract immediateunsigned instruction; a load upper immediate instruction; and an ORimmediate instruction.